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In-System Programmable 3.3V SuperWIDE™ High Density PLD
| Hersteller : | Lattice Semiconductor Corp |
|---|---|
| Verpackung/Behälter : | TQFP128 |
| Produkt der Kategorien : | SuperWIDE High Density PLD |
| Datasheet: | ISPLSI5128VE-100LTN128-80I Datasheet (PDF) |
| RoHs Status: | Lead free / RoHS Compliant |
| Lagerbestand: | 137 |
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ISPLSI5128VE-100LTN128-80I Beschreibung
The ispLSI 5000VE Family of In-System Programmable High Density Logic Devices is based on Generic Logic Blocks (GLBs) of 32 registered macrocells and a single Global Routing Pool (GRP) structure interconnecting the GLBs.
Outputs from the GLBs drive the Global Routing Pool (GRP) between the GLBs. Switching resources are provided to allow signals in the Global Routing Pool to drive any or all the GLBs in the device. This mechanism allows fast, efficient connections across the entire device.
Each GLB contains 32 macrocells and a fully populated, programmable AND-array with 160 logic product terms and three extra control product terms. The GLB has 68 inputs from the Global Routing Pool which are available in both true and complement form for every product term. The 160 product terms are grouped in 32 sets of five and sent into a Product Term Sharing Array (PTSA) which allows sharing up to a maximum of 35 product terms for a single function. Alternatively, the PTSA can be bypassed for functions of five product terms or less. The three extra product terms are used for shared controls: reset, clock, clock enable and output enable.
The 32 registered macrocells in the GLB are driven by the 32 outputs from the PTSA or the PTSA bypass. Each macrocell contains a programmable XOR gate, a programmable register/latch and the necessary clocks and control logic to allow combinatorial or registered operation. The macrocells each have two outputs, combinatorial and registered. This dual output capability from the macrocell allows efficient use of the hardware resources. One output can be a registered function for example, while the other output can be an unrelated combinatorial function. A direct register input from the I/O pad facilitates efficient use of this feature to construct high-speed input registers.
Macrocell registers can be clocked from one of several global or product term clocks available on the device. A global and product term clock enable is also available to each register, eliminating the need to gate the clock to the macrocell registers. Reset for the macrocell register is provided from the global signal, its polarity is userselectable. The macrocell register can be programmed to operate as a D-type register or a D-type latch.
The 32 outputs from the GLB can drive both the Global Routing Pool and the device I/O cells. The Global Routing Pool contains one input from each macrocell output and one input from each I/O pin.
The input buffer threshold has programmable TTL/3.3V/ 2.5V compatible levels. The output driver can source 4mA and sink 8mA in 3.3V mode. The output drivers have a separate VCCIO reference input which is independent of the main VCC supply for the device. This feature allows individual output drivers to drive either 3.3V (from the device VCC) or 2.5V (from the VCCIO pin) output levels while the device logic and the output current drive are powered from device supply (VCC). The output drivers also provide individually programmable edge rates and open drain capability. A programmable pullup resistor is provided to tie off unused inputs. Additionally, a programmable bus-hold latch is available to hold tristate outputs in their last valid state until the bus is driven again by some device.
The ispLSI 5000VE Family features 3.3V, non-volatile insystem programmability for both the logic and the interconnect structures, providing the means to develop truly reconfigurable systems. Programming is achieved through the industry standard IEEE 1149.1-compliant Boundary Scan interface. Boundary Scan test is also supported through the same interface.
An enhanced, multiple cell security scheme is provided that prevents reading of the JEDEC programming file when secured. After the device has been secured using this mechanism, the only way to clear the security is to execute a bulk-erase instruction.
Feature
— 3.3V Power Supply
— User Selectable 3.3V/2.5V I/O
— 6000 PLD Gates / 128 Macrocells
— 96 I/O Pins Available
— 128 Registers
— High-Speed Global Interconnect
— SuperWIDE Generic Logic Block (32 Macrocells) for Optimum Performance
— SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc.
— Interfaces with Standard 5V TTL Devices
• HIGH PERFORMANCE E2 CMOS® TECHNOLOGY
— fmax = 180 MHz Maximum Operating Frequency
— tpd = 5.0 ns Propagation Delay
— TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path Optimization
• IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
• 100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE
• ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture with SingleLevel Global Routing Pool and SuperWIDE GLBs
— Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell
— Macrocells Support Concurrent Combinatorial and Registered Functions
— Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable
— Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks
— Programmable I/O Supports Programmable Bus Hold, Pull-up, Open Drain and Slew Rate Options
— Four Global Product Term Output Enables, Two Global OE Pins and One Product Term OE per Macrocell
(Bild: Diagram)
Technische Parameter
- Hersteller
- LATTICE
- Verpackung
- Tape & Reel (TR)/Cut Tape (CT)/Tray/Tube
- RoHs Status
- Lead free / RoHS Compliant
- Verpackung/Behälter
- TQFP128
ISPLSI5128VE-100LTN128-80I Datasheet
-
ispLSI5128VE
ISPLSI5128VE-100LTN128-80I Verwandte besondere
Bewertungen und Rezensionen (1)
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- 5 Stars 100%
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**URI ***2020-03-18
excellent item - thank you ☺️
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1.The electronic components you purchase include 365 Days Warranty, We guarantee product quality.
2.If some of the items you received aren't of perfect quality, we would resiponsibly arrange your refund or replacement. But the items must remain their orginal condition.
FAQ:
- Q: How does Jotrin guarantee that ISPLSI5128VE-100LTN128-80I is the original manufacturer or agent of LATTICE?
- We have a professional business development department to strictly test and verify the qualifications of LATTICE original manufacturers and agents. All LATTICE suppliers must pass the qualification review before they can publish their ISPLSI5128VE-100LTN128-80I devices; we pay more attention to the channels and quality of ISPLSI5128VE-100LTN128-80I products than any other customer. We strictly implement supplier audits, so you can purchase with confidence.
- Q: How to find the detailed information of ISPLSI5128VE-100LTN128-80I chips? Including LATTICE original factory information, SuperWIDE High Density PLD application, ISPLSI5128VE-100LTN128-80I pictures?
- You can use Jotrin's intelligent search engine, or filter by SuperWIDE High Density PLD category, or find it through Lattice Semiconductor Corp Information page.
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Yes. We accept offline orders.
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Note: It may take up to 24 hours before carriers will display tracking information. In normal conditions, Express delivery needs 3-5 days, Registered Mail needs 25-60 days. - Q: What is the process for returns or replacement of ISPLSI5128VE-100LTN128-80I?
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All goods will implement Pre-Shipment Inspection (PSI), selected at random from all batches of your order to do a systematic inspection before arranging the shipment.
If there is something wrong with the ISPLSI5128VE100LTN12880I we delivered, we will accept the replacement or return of the ISPLSI5128VE-100LTN128-80I only when all of the below conditions are fulfilled:
(1)Such as a deficiency in quantity, delivery of wrong items, and apparent external defects (breakage and rust, etc.), and we acknowledge such problems.
(2)We are informed of the defect described above within 90 days after the delivery of ISPLSI5128VE-100LTN128-80I.
(3)The ISPLSI5128VE-100LTN128-80I is unused and only in the original unpacked packaging.
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(1)Inform us within 90 days
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More details about return electronic components please see our Return & Change Policy. - Q: How to contact us and get support, such as ISPLSI5128VE-100LTN128-80I datasheet pdf, ispLSI5128VE pin diagram?
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