Produkte > Integrierte Schaltungen (ICs) > Programmierbare Logik-ICs > M5-512/256-10SAI

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M5-512/256-10SAI

CPLD MACH 5 Family 20K Gates 512 Macro Cells 66.7MHz/100MHz 5V 352-Pin BGA Tray

Hersteller : Lattice Semiconductor Corp
Verpackung/Behälter : BGA-256
Produkt der Kategorien : CPLD - Complex Programmable Logic Devices
Datasheet: M5-512/256-10SAI Datasheet (PDF)
RoHs Status: Lead free / RoHS Compliant
Lagerbestand: 210

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M5-512/256-10SAI Beschreibung

The MACH® 5 family consists of a broad range of high-density and high-I/O Complex Programmable Logic Devices (CPLDs). The fifth-generation MACH architecture yields fast speeds at high CPLD densities, low power, and supports additional features such as in-system programmability, Boundary Scan testability, and advanced clocking options . The MACH 5 family offers 5-V (M5-xxx) and 3.3-V (M5LV-xxx) operation. 

Manufactured in state-of-the-art ISO 9000 qualified fabrication facilities on E2CMOS process technologies, MACH 5 devices are available with pin-to-pin delays as fast as 5.5 ns . The 5.5, 6.5, 7.5, 10, and 12-ns devices are compliant with the PCI Local Bus Specification.

With Lattice’s unique hierarchical architecture, the MACH 5 family provides densities up to 512 macrocells to support full system logic integration. Extensive routing resources ensure pinout retention as well as high utilization. It is ideal for PAL® block device integration and a wide range of other applications including high-speed computing, low-power applications, communications, and embedded control. At each macrocell density point, Lattice offers several I/O and package options to meet a wide range of design needs.

Advanced power management options allow designers to incrementally reduce power while maintaining the level of performance needed for today’s complex designs. I/O safety features allow for mixed-voltage design, and both the 3.3-V and the 5-V device versions are in-system programmable through an IEEE 1149.1 Test Access Port (TAP) interface.

M5-512/256-10SAI

Feature

◆ High logic densities and I/Os for increased logic integration 

— 128 to 512 macrocell densities 

— 68 to 256 I/Os 

◆ Wide selection of density and I/O combinations to support most application needs 

— 6 macrocell density options 

— 7 I/O options 

— Up to 4 I/O options per macrocell density 

— Up to 5 density & I/O options for each package 

◆ Performance features to fit system needs 

— 5.5 ns tPD Commercial, 7.5 ns tPD Industrial 

— 182 MHz fCNT 

— Four programmable power/speed settings per block 

◆ Flexible architecture facilitates logic design 

— Multiple levels of switch matrices allow for performance-based routing 

— 100% routability and pin-out retention 

— Synchronous and asynchronous clocking, including dual-edge clocking 

— Asynchronous product- or sum-term set or reset 

— 16 to 64 output enables 

— Functions of up to 32 product terms 

◆ Advanced capabilities for easy system integration 

— 3.3-V & 5-V JEDEC-compliant operations 

— IEEE 1149.1 compliant for boundary scan testing 

— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port 

— PCI compliant (-5/-6/-7/-10/-12 speed grades) 

— Safe for mixed supply voltage system design 

— Bus-Friendly™ Inputs & I/Os 

— Individual output slew rate control 

— Hot socketing 

— Programmable security bit

◆ Advanced E2CMOS process provides high performance, cost effective solutions 

◆ Supported by ispDesignEXPERT™ software for rapid logic development 

— Supports HDL design methodologies with results optimized for MACH 5 devices 

— Flexibility to adapt to user requirements 

— Software partnerships that ensure customer success 

◆ Lattice and Third-party hardware programming support 

— LatticePRO™ software for in-system programmability support on PCs and Automated Test Equipment 

— Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General

M5-512/256-10SAI Block Diagram
(Bild: Diagram)

Technische Parameter

  • Memory Type
  • EEPROM
  • Number of Macrocells
  • 512
  • Maximum Operating Frequency
  • 100 MHz, 125 MHz
  • Delay Time
  • 10 ns
  • Number of Programmable I/Os
  • 256
  • Operating Supply Voltage
  • 4.5 V to 5.5 V
  • Maximum Operating Temperature
  • + 85 C
  • Minimum Operating Temperature
  • - 40 C
  • Package / Case
  • BGA-256
  • Mounting Style
  • SMD/SMT
  • Number of Product Terms per Macro
  • 32
  • Packaging
  • Tray
  • Factory Pack Quantity
  • 120
  • Supply Voltage Max
  • 5.5 V
  • Supply Voltage Min
  • 4.5 V

M5-512/256-10SAI Datasheet

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Q: How does Jotrin guarantee that M5-512/256-10SAI is the original manufacturer or agent of LATTICE?
We have a professional business development department to strictly test and verify the qualifications of LATTICE original manufacturers and agents. All LATTICE suppliers must pass the qualification review before they can publish their M5-512/256-10SAI devices; we pay more attention to the channels and quality of M5-512/256-10SAI products than any other customer. We strictly implement supplier audits, so you can purchase with confidence.
Q: How to find the detailed information of M5-512/256-10SAI chips? Including LATTICE original factory information, CPLD - Complex Programmable Logic Devices application, M5-512/256-10SAI pictures?
You can use Jotrin's intelligent search engine, or filter by MACH 5 CPLD Family category, or find it through Lattice Semiconductor Corp Information page.
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Q: What is the process for returns or replacement of M5-512/256-10SAI?
All goods will implement Pre-Shipment Inspection (PSI), selected at random from all batches of your order to do a systematic inspection before arranging the shipment. If there is something wrong with the M551225610SAI we delivered, we will accept the replacement or return of the M5-512/256-10SAI only when all of the below conditions are fulfilled:
(1)Such as a deficiency in quantity, delivery of wrong items, and apparent external defects (breakage and rust, etc.), and we acknowledge such problems.
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Lattice Semiconductor Corp

Lattice
Lattice Semiconductor Corporation is a leading provider of Programmable Logic Devices, software, Intellectual Property, and development kits. The Mid-Range Lattice ECP3 family is the lowest power SerDes enabled FPGA available in the market. The MachXO is the most versatile non-volatile PLD targeted...
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