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Interface - Signal Buffers, Repeaters Level Translating I2 C-Bus Repeater
| Hersteller : | NXP Semiconductor |
|---|---|
| Verpackung/Behälter : | TSSOP-8 |
| Produkt der Kategorien : | Interface - Signal Buffers, Repeaters |
| Datasheet: | PCA9617ADPJ Datasheet (PDF) |
| RoHs Status: | Lead free / RoHS Compliant |
| Lagerbestand: | 15000 |
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PCA9617ADPJ Beschreibung
General description
The PCA9617ADPJ is a CMOS integrated circuit that provides level shifting between low voltage (0.8 V to 5.5 V) and higher voltage (2.2 V to 5.5 V) Fast-mode Plus (Fm+) I2C-bus or SMBus applications. While retaining all the operating modes and features of the I 2C-bus system during the level shifts, it also permits extension of the I2C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 540 pF at 1 MHz or up to 4000 pF at lower speeds. Using the PCA9617ADPJ enables the system designer to isolate two halves of a bus for both voltage and capacitance. The SDA and SCL pins are overvoltage tolerant and are high-impedance when the PCA9617ADPJ is unpowered.
The 2.2 V to 5.5 V bus port B drivers have the static level offset, while the adjustable voltage bus port A drivers eliminate the static offset voltage. This results in a LOW on the port B translating into a nearly 0 V LOW on the port A which accommodates the smaller
voltage swings of lower voltage logic.
The static offset design of the port B PCA9617ADPJ I/O drivers prevents them from being connected to the static or incremented offset of other bus buffers. Port A of two or more PCA9617As can be connected together, however, to allow a star topography with port A on the common bus, and port A can be connected directly to any other buffer with static or incremented offset outputs. Multiple PCA9617As can be connected in series, port A to port B, with no build-up in offset voltage with only time of flight delays to consider.
The PCA9617ADPJ drivers are not enabled unless VCC(A) is above 0.8 V and VCC(B) is above 2.2 V. The EN pin is referenced to VCC(B) and can also be used to turn the drivers on and off under system control. Caution should be observed to only change the state of the
enable pin when the bus is idle.
The output pull-down on the port B internal buffer LOW is set for approximately 0.55 V, while the input threshold of the internal buffer is set about 90 mV lower (0.45 V). When the port B I/O is driven LOW internally, the LOW is not recognized as a LOW by the input. This prevents a latching condition from occurring. The output pull-down on port A drives a hard LOW and the input level is set at 0.35VCC(A) to accommodate the need for a lower LOW level in systems where the low voltage side supply voltage is as low as 0.8 V.
The PCA9617ADPJ is a CMOS integrated circuit that provides level shifting between low voltage (0.8 V to 5.5 V) and higher voltage (2.2 V to 5.5 V) Fast-mode Plus (Fm+) I2C-bus or SMBus applications. While retaining all the operating modes and features of the I 2C-bus system during the level shifts, it also permits extension of the I2C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 540 pF at 1 MHz or up to 4000 pF at lower speeds. Using the PCA9617ADPJ enables the system designer to isolate two halves of a bus for both voltage and capacitance. The SDA and SCL pins are overvoltage tolerant and are high-impedance when the PCA9617ADPJ is unpowered.
The 2.2 V to 5.5 V bus port B drivers have the static level offset, while the adjustable voltage bus port A drivers eliminate the static offset voltage. This results in a LOW on the port B translating into a nearly 0 V LOW on the port A which accommodates the smaller
voltage swings of lower voltage logic.
The static offset design of the port B PCA9617ADPJ I/O drivers prevents them from being connected to the static or incremented offset of other bus buffers. Port A of two or more PCA9617As can be connected together, however, to allow a star topography with port A on the common bus, and port A can be connected directly to any other buffer with static or incremented offset outputs. Multiple PCA9617As can be connected in series, port A to port B, with no build-up in offset voltage with only time of flight delays to consider.
The PCA9617ADPJ drivers are not enabled unless VCC(A) is above 0.8 V and VCC(B) is above 2.2 V. The EN pin is referenced to VCC(B) and can also be used to turn the drivers on and off under system control. Caution should be observed to only change the state of the
enable pin when the bus is idle.
The output pull-down on the port B internal buffer LOW is set for approximately 0.55 V, while the input threshold of the internal buffer is set about 90 mV lower (0.45 V). When the port B I/O is driven LOW internally, the LOW is not recognized as a LOW by the input. This prevents a latching condition from occurring. The output pull-down on port A drives a hard LOW and the input level is set at 0.35VCC(A) to accommodate the need for a lower LOW level in systems where the low voltage side supply voltage is as low as 0.8 V.
Feature
- Footprint and functional replacement
- Active high repeater enable input referenced to VCC(B)
- Open-drain input/outputs
- Latching free operation
- Supports arbitration and clock stretching across the repeater
- Powered-off high-impedance I²C pins
- ESD protection exceeds 5500V HBM per JESD22-A114 and 1000V CDM per JESD22-C101
- Latch-up testing is done to JEDEC standard JESD78 which exceeds 100mA
(Bild: Pinout)
Technische Parameter
- Product Type
- Repeaters
- Maximum Clock Frequency
- 1 MHz
- Operating Supply Voltage
- 2.2 V to 5.5 V
- Operating Temperature Range
- - 40 C to + 85 C
- Mounting Style
- SMD/SMT
- Package / Case
- TSSOP-8
- Input Capacitance
- 7 pF
- Logic Type
- I2C Bus
- Operating Current
- 8 uA
- Power Dissipation
- 100 mW
- Series
- PCA9617A
- Tx/Rx Type
- I2C
PCA9617ADPJ Datasheet
-
PCA9617A NXP Technical Data
PCA9617ADPJ Verwandte besondere
Ratings and Reviews (1)
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- 5 Stars 100%
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**schw***2020-03-28
Alles Super immer wieder!!
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2.If some of the items you received aren't of perfect quality, we would resiponsibly arrange your refund or replacement. But the items must remain their orginal condition.
FAQ:
- Q: How does Jotrin guarantee that PCA9617ADPJ is the original manufacturer or agent of NXP?
- We have a professional business development department to strictly test and verify the qualifications of NXP original manufacturers and agents. All NXP suppliers must pass the qualification review before they can publish their PCA9617ADPJ devices; we pay more attention to the channels and quality of PCA9617ADPJ products than any other customer. We strictly implement supplier audits, so you can purchase with confidence.
- Q: How to find the detailed information of PCA9617ADPJ chips? Including NXP original factory information, Interface - Signal Buffers, Repeaters application, PCA9617ADPJ pictures?
- You can use Jotrin's intelligent search engine, or filter by Interfaces ; I2C, SPI, Serial Interface Devices ; I2C-bus Repeaters/Hubs/Extenders category, or find it through NXP Semiconductor Information page.
- Q: Are the NXP's PCA9617ADPJ price and stock displayed on the platform accurate?
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All goods will implement Pre-Shipment Inspection (PSI), selected at random from all batches of your order to do a systematic inspection before arranging the shipment.
If there is something wrong with the PCA9617ADPJ we delivered, we will accept the replacement or return of the PCA9617ADPJ only when all of the below conditions are fulfilled:
(1)Such as a deficiency in quantity, delivery of wrong items, and apparent external defects (breakage and rust, etc.), and we acknowledge such problems.
(2)We are informed of the defect described above within 90 days after the delivery of PCA9617ADPJ.
(3)The PCA9617ADPJ is unused and only in the original unpacked packaging.
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(1)Inform us within 90 days
(2)Obtain Requesting Return Authorizations
More details about return electronic components please see our Return & Change Policy. - Q: How to contact us and get support, such as PCA9617ADPJ datasheet pdf, PCA9617A pin diagram?
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