Design of ARINC429 Data Interface Card Based on FPGA Device and PCI9052 Chip
Veröffentlichte Zeit: 2020-03-30 12:17:07
In modern military, civil aircraft and missiles, a large amount of information needs to be transmitted between systems. With the development of digital technology and the emergence of microelectronic computers, more and more avionics have used aeronautical data buses for communication. Among them, ARINC429, as a digital information transmission system, has become the aviation industry standard for avionics communication. At present, the ARINC429 bus is widely used in the field of military science and technology. From fighter jets to helicopters are even used in missile systems. Among the existing products, the ARINC429 circuit form has its own characteristics. The interfaces are based on PCI, ISA, PC / 104 and VXI, and the on-board processors are MCS-51, Intel80196, Intel80386, FPGA, etc. The functions are numerous and the use is complicated It is bound to result in expensive data communication boards. Although the design using FPGA field programmable gate array can simplify the hardware design, it is difficult to develop and the cycle is long. Based on the characteristics of various schemes, this paper proposes an ARINC429 data interface implementation scheme based on PCI interface and DSP as the main control CPU with short cycle, low cost and high practical value, and briefly introduces the software and hardware implementation.
1.Introduction of ARINC429 bus
ARINC429 is a unidirectional broadcast digital bus. The transmission medium is composed of twisted pair wires, which essentially belongs to the category of serial communication. The system stipulates that two-way transmission of data information is not allowed on a pair of transmission lines. The modulation method uses the bipolar return-to-zero (BPRZ) tri-state code method. The data is transmitted through a two-stage differential drive, as shown in Figure 1. , V- is the TTL level, ARINC429's normal transmission voltage is in the range of 10 ± 1 V, and there is a difference between positive and negative voltages. The signal level range can represent 3 states. The logic “1” level voltage is 7.25: 11V (AB Between), logic "0" level voltage-7.25: -11 V (between AB), and empty state level voltage -0.5: 0.5 V (between AB). When continuously transmitting data, At least a null state is inserted for isolation, and the bus data transmission sequence is 1,2,3,4,5,6,7,8,9,10,11,12,13 ... 32.
2. Overall scheme design
The main function of the ARINC429 bus interface card is to act as a bridge between the ARINC429 bus and the PCI bus, to realize the receiving and sending of data information of the 429 bus. The overall design idea of this article is: select TI's TMS320LF2407 as the main control CPU; use ARINC429 special chip DEI1016 and BD429 as the core to design the ARINC429 bus communication module to complete the data sending and receiving tasks; the CPU and computer data exchange uses the PCI bus, in order to shorten development Time and difficulty, using PCI special interface chip PCI9052 to achieve.
2.1 Selection of CPU module
TMS320LF2407 is a low-cost, high-performance control-oriented 16-bit fixed-point DSP launched by TI. Its on-chip 32K Flash, 2k-word SRAM, and 544-word DARAM can save off-chip hardened memory and simplify the interface circuit design. TMS320L22407 has 40 Each can be individually programmed or multiplexed with a general-purpose IO port, which can partially control the 429 transceiver chip.
2.2 429 bus interface circuit
At present, ARINC429 transceivers are the most widely used by Device Engineering's DEI1016 and BD429 and HARRIS's HS3282 and HS3281. The two chips are fully compatible logically. DEI1016 is a high-performance COMS 429 interface that can meet similar time-division multiplexed serial data For communication, the entire chip only needs a single 5 V working power supply. It has two receivers and one transmitter. The receiver and transmitter are independent of each other and work at the same time. BD429 is a line driver with bipolar data input that meets the ARINC429 specification.
2.3 data buffer
The DSP and PCI bridge chip realize real-time data transmission. This design chooses the communication mode of dual-port RAM. The dual-port RAM has two sets of completely independent data, address and control buses. It contains a bus arbitration circuit inside, which can realize the connection between the PCI bus and the DSP. High-speed data buffering and exchange.
2.4 The overall design of the system
Because PCI9052 is a dedicated bridge chip for the PCI bus, only the address, data, control, and status signal lines related to the PCI bus on the PCI9052 chip need to be directly connected to the computer's PCI bus on the hardware connection of the PCI side. For the DSP, the dual-port RAM is used as the LF2407 off-chip data memory, which needs to be mapped to the off-chip data space address from 8000h to FFFFh. As shown in Figure 4, the dual-port RAM chip is selected only when valid and A15 is high. At this time, the address of the off-chip data space occupied by the DSP is 8000h to FFFFh. On the side of PCI9052, because the IDT7027 data bus is 16-bit, the PCI9052 local bus is configured as a 16-bit wide data bus when the EEPROM is configured. Section (8bit) addressing, the local bus is addressed by words (16bit), so the dual-port RAM address line AL [14: 1] is provided by the PCI9052 local end address bus LA [15: 2], and the AID is provided separately by LBE1. This completes the one-to-one correspondence between the data storage space and the address, the system decodes, and the level conversion is implemented using CPLD.
3. Software design
3.1 PCI device driver
This ARINC429 interface card is a PCI device. You must develop the driver of the PCI device yourself under Windows. The driver is written with WinDriver. It uses the general device drivers Windrvr.vxd and Windrvr.sys as the core and contains a WinDriver Wizard code. Generator, a WinDriver distribution package. This software has specially written API function packages for the special interface chips of PLX and AMCC. These functions can conveniently implement interrupt processing, DMA transfers, I / O operations, memory mapping, and plug and play. Functions, which facilitate the development of system programs and reduce the difficulty.
3.2 DSP control program
The upper computer program writes the data block to be sent to the dual-port RAM through the PCI bus and informs the DSP to read the information. Since the PCI side corresponds to the RAM address on the DSP side, the DSP only needs to read at the corresponding memory address. The corresponding information completes the initialization of the DSP, the configuration of the DEI1016, and the sending and receiving of its 429 data.
It can be seen from the entire design scheme that the main function chips are selected by dedicated chips to complete the data communication between the 429 bus and the PCI bus using a DSP, eliminating the need for peripheral circuits such as EPROM, RAM, and latches. The design is simple, effective, and reliable, and the reasonable use of CPLDs enhances the integration of the board. The interface card has been tested with a certain missile product laboratory to prove that its design can meet the ARINC429 data transmission requirements. The communication protocol frame number and sending cycle are flexibly customized through DSP, which reduces the complexity of application development, and the data transmission is fast and reliable. High reliabilityEtikett: PCI9052