NASA Selects SiFive RISC-V CPUs to Power Future Space Computers

Among the new applications that RISC-V is gradually opening up, we are familiar with AIoT, automotive, and HPC, which is quite impressive for a new architecture to expand its footprint. However, in the space sector, even Arm or x86 dare not claim to be widely used in this market, but the new player, RISC-V, is starting to be seen by the space sector in various countries.

NASA's chosen ecosystem of choice for space missions

Chip designer SiFive said Tuesday its RISC-V-compatible CPU cores will power NASA's just-announced High-Performance Spaceflight The HPSC will be used in all future space missions, from planetary exploration to lunar and Mars surface missions and more, and will use eight SiFiveIntelligence X280 RISC-V vector cores, as well as four additional SiFiveRISC-V cores.

Intelligence X280 architecture diagram/SiFive

Although exactly what the four additional RISC-V cores will be is not specified, SiFive says that the HPSC in this configuration will provide 100 times the computing power of today's space computers. Such a performance increase will provide new opportunities for various critical space missions, such as rover autopilot, vision processing, space flight, space navigation systems, communications and other applications.

PolarFire® SoC FPGA Icicle Kit / Microchip

Although SiFive's RISC-V core was selected, Microchip is responsible for building this computing platform. In August of this year, NASA gave Microchip the task of architecting, designing and delivering the HPSC processor within three years. The current Microchip product lineup already has a radiation-resistant space FPGA. The product RT PolarFire, Microchip's PolarFireSoC FPGA processor subsystem, also uses SiFive's four U54 cores and one E51 core. Hence, NASA's choice of SiFive as the IP supply is more than reasonable.

As for the chip used for comparison, it should be the RAD750 used for the Mars rover Trail and the James Webb Space Telescope, a PowerPC processor launched in 2001, the maximum frequency is only 200MHz, the maximum operating speed is only 2.66 MIPS, the new HPSC is justifiable to leave a big cut off.

NASA's second RISC-V attempt

As early as 2018, NASA's Goddard Space Center, the research organization responsible for managing the Hubble Space Telescope, has carried out RISC-V-related research projects. Their idea for considering RISC-V at the time was simple. With the increasing usage of IP core-based FPGA processor systems, an open-source architecture like RISC-V architecture can potentially reduce the overall cost of data systems.

For NASA's cFE/CFS (Core Flight Processor System) software, which has open source-related collaborations, RISC-V, as an open-source architecture, could be a perfect fit. Porting the cFE/CFS to the RISC-V architecture will significantly reduce development cycles and time and facilitate using RISC-V processor solutions for future missions. Using the RISC-V architecture and its open source tools would eliminate high IP costs and no longer be limited to a single vendor.

Unfortunately, however, the project appears to have ended in 2019, staying in the application research phase, and RISC-V was not actually used on NASA's vehicle data systems. After all, from 2018 to 2019, the development ecology and IP ecology of RISC-V were not as well developed as it is today, and now that IP vendors and FPGA vendors have joined the ecological cooperation of RISC-V, it is inevitable that NASA will reselect RISC-V.

RISC-V began to take over the aerospace chip

In fact, many chips in the field of aerospace chips are based on the SPARC architecture, especially the LEON processor IP used by the European Space Agency, but this is a thing of the past, the European Space Agency has now turned to RISC-V, RISC-V has also been in the sky once. The TRISTAN-R satellite, which lifted off this year, has its on-board computer NANOhpm integrated with NOEL-V processor IP, Cobham Gaisler's latest RISC-V IP and the successor to their previous generation SPARCv8 product LEON5.

NOEL-V features a dual-launch, 8-stage pipeline design that runs on complex operating systems with performance comparable to Arm's CortexA53 and is suitable for integration in FPGAs and ASICs. For use in aerospace missions, a highly fault-tolerant version of this processor core was introduced, allowing on-chip memory to be protected from radiation effects, as errors generated by radiation can be handled on the fly without affecting the software's real-time work.

Many of the electronic SoCs from the famous Chinese aerospace chip company, Orbita Aerospace, are also based on SPARCv8 and have reached leading international levels in terms of performance and reliability. However, judging from the new product launched by Orbita Aerospace, Yulong 810 AI chip, they may choose to turn to Arm in this direction.

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