SX1262 chip module detailed introduction
Veröffentlichte Zeit: 2020-12-29 15:11:26
SX1262 is a new sub-GHz wireless transceiver launched by Semtech. The biggest buying point of the SX1262 chip is its low power consumption and ultra-long-distance transmission. SX1261 and SX1262 chip work frequency range covers 150~960HMZ. SX1261 can transmit up to +15 dBm, while SX1262 can transmit up to +22 dBm. The receiving current of SX1262 is less than 6.5mA, the lowest can be less than 4.2mA, and the sleep current is 0.9~2.35, realizing a low power consumption chip in a true sense; and its ultra-long transmission distance of 5km is also the embodiment of the powerful functions of the SX1262 chip. There is a TCXO crystal oscillator inside to ensure accurate frequency.
The working frequency band of the SX1262 chip covers 150~960HMZ, and there are four main parts of this wireless transceiver:
Analog front end: transmit and receive chain and data converter interface with subsequent digital modules, the chip can provide up to +22 dBm transmit power under battery power.
Digital modem group: SX1262 chip provides a series of modulation options: LoRa Rx/Tx, BW = 7.8-500 kHz, SF5 to SF12, BR = 0.018-62.5 kb / s
(G) FSK Rx / Tx, BR = 0.6-300 kb / s. (SX1262 has two modulation methods: lora and (G) FSK)
Digital interface and control: This includes all payload data and protocol processing and access to configure the radio via the SPI interface.
Power distribution: Two forms of voltage regulation can be provided, DC-DC, or linear regulator LDO.
Digital interface and control
SX1262 is controlled through a serial SPI interface and a set of general-purpose input/output (DIO). At least one DIO must be used for IRQ and BUSY lines are required to ensure that the host controller is ready to accept commands. The SX1262 uses an internal controller (CPU) to handle communication and chip control (mode switching, API, etc.). Busy is used as a busy signal, which means that the chip is only ready to receive new commands when the signal is low. When BUSY is high, the host controller must wait until it shuts down again before sending another command. Send commands to the internal chip through the SPI application program or directly access the data storage space.
By switching the pin 15 RESET of SX12612, a complete "factory reset" of the chip can be issued upon request. This will automatically follow the standard calibration procedure and any previous context will be lost. When the pin reset occurs, the low level exceeds 50μs (usually 100μs).
The SPI interface accesses the configuration registers through the synchronous full-duplex protocol corresponding to CPOL = 0 and CPHA = 0 in Motorola / Freescale nomenclature. Only implement subordinate parties. Send an address byte followed by a data byte for write access, and send an address byte and receive a read byte for reading access. The NSS pin goes low at the beginning of the frame and goes high after the data byte. MOSI is generated by the host on the falling edge of SCK, and the edge of SCK is sampled by the slave (that is, the SPI interface) when it is rising. MISO is generated by the slave on the falling edge of SCK. The transfer is always started by turning the NSS pin low. When NSS is high, MISO is high impedance. SPI runs on the external SCK clock at a rate up to 16 MHz.
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