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Startseite > Other > What steps are needed to make a chip ?

What steps are needed to make a chip ?

Updatezeit: 2022-08-17 18:28:14

What steps are needed to make a chip ?

Chip design

Many people will compare the process of manufacturing chips to building a building, so what is the first and most important step? Of course, the building is also the design of the chip. In other words, the chip design is the basis for a good chip. Even if the downstream manufacturing, packaging and testing capabilities are strong and unbeatable, there are no design plans for nothing.

As one of the world's most subtle but also the most ambitious engineering, chip design is never as simple as drawing a picture on a computer. Generally speaking, the chip design phase can be divided into four major processes: specification definition, system-level design, front-end design and back-end design.

1. Specification definition

Specification definition is the engineer at the beginning of the chip design, chip requirements analysis, to determine the chip cost control at what level, the purpose and performance, to complete the product specification definition, to determine the overall direction of the design. Then look at the need to comply with the agreement; otherwise, the chip will not be compatible with the products on the market and can not be connected to other devices. Finally, the chip's implementation method is established, allocating different functions into different units, and establishing the connection method between different units, so the specification is completed. The purpose of the chip specification definition is to ensure that the designed chip will not have any errors.

2. System-level design

Since the chip design has to consider the system interaction, function, cost, power consumption, performance, security, and maintainability, engineers need to develop design solutions and specific implementation architecture design based on the preliminary specification definition, divide the module function, clarify the chip architecture, business module, power supply and other system-level design, such as CPU, GPU, NPU, RAM, connection, interface, etc.

3. Front-end design

Chip front-end design, also known as logic design, can be said to be the soul of the entire chip design phase, the real realization of the chip from scratch process, so the chip front-end design engineers have become the most sought-after type of talent in the industry, the salary naturally also rose, of course, these are off-topic. So what does the front-end design work mainly include?

Front-end design is the engineer according to the system design to determine the scheme, for each module to carry out specific circuit design, the use of Verilog or VHDL code (hardware description language), the specific circuit implementation of the RTL (Register Transfer Level) level code description. Simply put, this means that the module functions are described in code, i.e., the actual hardware circuit functions are described in HDL to form RTL code. And behind the code corresponds to the circuit, so the front-end design engineer needs to know what kind of circuit will become behind the code when writing the code.

Once the code is generated, it needs to be simulated and verified, and the correctness of the code design is repeatedly verified through simulation in strict accordance with the developed specification standards. Verification is the most time-consuming and labour-intensive process in chip design, and according to ARM technical white papers, 40% of a project's resources are spent on the verification phase.

After verification, logic synthesis is performed, using EDA tools to turn the register transfer level design RTL description into a Netlist to ensure that the circuit meets standards regarding the area, timing, and other target parameters. Static timing analysis is then performed, applying a specific timing model to the specific circuit to analyze whether it violates the design's timing constraints.

The front-end design process does not happen overnight. It requires engineers to repeatedly synthesize, verify, and check various design rules to ensure the design's correctness and that the design's layout wiring is feasible and optimized.

4. Back-end design

Back-end design is the realization of the front-end design. Specifically, the logical synthesis into the physical netlist and then into the manufacturing plant can be used to manufacture photomask graphics files.

The first thing to do is DFT (Design For Test), that is, the design for testability, the chip often comes with its own internal test circuit, you need to pre-plan and insert a variety of logic circuits for chip testing.

Next is the layout planning, placing the chip's macro cell module, in general, to determine the placement of various functional circuits, such as IP modules, RAM, I/O pins, etc. The area of the chip, timing convergence, stability, alignment difficulties, etc., will be affected by the channel layout planning.

Then comes the clock tree synthesis, the clock wiring to connect the various components. Since the clock signal plays a global command role in the digital chip, symmetrically connected to each register cell so that the clock arrives at each register from the same clock source with minimal difference in clock delay, separate wiring is often required.

The clock wiring is followed by general signal wiring, including the alignment between various standard cells (basic logic gate circuits); the extraction of parasitic parameters and re-analysis to verify signal integrity issues; and various verifications and the generation of the GDS layout for chip production.

As the last step before chip production, back-end design often faces more challenges and tight deadlines in the actual design. Its importance is increasingly highlighted as the complexity of layout and wiring grows after entering the nano era. However, for some small and medium-sized design companies, a good back-end design team and minimal capital expenditure are like "fish" and "bear's paw", which cannot be combined. But suppose there is no back-end design and only relies on front-end engineers. In that case, the lack of project experience may cause a lot of duplication of work and even affect the chip's final performance and power consumption. In this context, finding the best fulcrum between the two so that capital expenditure obtains the highest return efficiency has become the key. This fulcrum is difficult to achieve only by the enterprise, the need for professional team support.

Many chip companies hand over back-end design to chip design services companies. Yes, here appears another industry chain division of labour, chip design service companies, neither chip design companies nor the following wafer manufacturing enterprises, but it is the inevitable product of the development of the chip industry under the flood between chip design companies and fabs to build an important bridge, like today's familiar creative electronics, VeriSilicon shares, Moore Elite, Zhiyuan Technology, Cancer Semiconductor, etc. are part of Chip design service companies.

It can be said that chip design services in the chip industry chain play the role of a chip design foundry centre for chip design companies, especially start-up design companies, have great value, and their perfect back-end design services are one of the important value. Generally speaking, chip design service companies have rich experience in back-end design. For example, Creative Electronics, as a full-flow custom IC design service company, is also very professional in the digital back-end (DFT, STA, APR) and can provide extended DFT services. Moore Elite is a leading one-stop chip design and supply chain service platform in China, committed to "making China's chips not difficult to make"; in the field of chip design services, Moore Elite provides ASIC design and Turnkey solutions, and its stable back-end design team has rich experience in SoC design and project management. With extensive experience in SoC design and project management, its stable back-end design team can provide digital back-end design for advanced process nodes. While Canchip's business mainly includes IP and chip customization services, it also covers front-end to back-end, and its strength should not be underestimated.

As Moore's Law continues to develop, coupled with the development trend of miniaturization and integration, back-end design is becoming more and more complex and important. Unlike wealthy system vendors and Internet companies, start-up chip companies should know how to "lighten up" with the lowest possible risk and cost to bring the chip to market quickly.

Chip manufacturing

Chip manufacturing is key in turning chips from drawings into physical objects. Still, another important step is before the mass production of chips, often referred to as pilot production.

The flow of chips for chip developers is equivalent to the examination for students. Students "smell the test change", and chip developers "smell the flow of chips change". This is because the cost of failure is too serious; a failed flow often means millions or even tens of millions of dollars in losses and at least six months of missed market opportunities. Many start-up chip companies are lost in the vast chip industry due to the failure of the chip's flow. And the reasons for the failure of the flow of the chip are also strange, maybe just VDD and GND installed backwards, maybe wet clean with the wrong liquid, in short, any small oversight may lead to the failure of the flow of the chip.

Back to the topic of chip manufacturing, how many steps why can make the enterprise "smell the flow of film change" in the end? It is understood that a chip production line involves about 2,000-5,000 processes, I may not be able to introduce all of them, so I can only introduce some key steps.

From a broad perspective, wafer production includes two major steps: wafer manufacturing and wafer manufacturing, plus the wafer pin testing process, collectively known as the wafer manufacturing process before, and the following will be introduced in the packaging and testing is called the wafer manufacturing process after.

1. Purification: After the sand/quartz is purified by deoxidation, the silicon dioxide with 25% silicon content is obtained, then refined by an electric arc furnace, chlorinated by hydrochloric acid, and distilled to obtain crystalline silicon with a purity of over 99%.

2. Rod manufacturing: The crystalline silicon is melted at high temperatures, and a complete rod is obtained by the rotational stretching method through neck growth, crown growth, crystal growth, and tail growth.

3. Slicing: The wafer is sliced horizontally into wafers of basically the same thickness by using a thin saw blade with diamond particles inlaid on the edge of its inner diameter in a ring shape.

4. Grinding and polishing: The wafer appearance is polished to remove the saw marks and damages produced on the wafer surface during cutting so that the wafer surface reaches the required finish.

5. Oxidation: The surface is oxidized and chemically vapour deposited, which can be used as an auxiliary layer for later processes and to help isolate electrical devices and prevent short circuits.

6. Photolithography and etching: A photoresist layer is spin-coated on the surface of the oxidized wafer, which is subsequently exposed, and then the circuit diagram is revealed through development. The circuit pattern is then transferred by chemical reaction or bombardment of the wafer surface with plasma.

7. Ion injection, annealing: bombarding the impurity ions into the semiconductor lattice and then heating the semiconductor after ion injection at a certain temperature to activate the different electrical properties of the semiconductor material.

8. Vapor deposition, electroplating: vapour deposition is used to form various metal layers as well as insulation layers, electroplating is dedicated to the growth of copper wire metal layer.

9. Chemical-mechanical grinding: A combination of chemical etching and mechanical grinding is used for grinding and polishing.

10. Finally, several layers of circuits and components are processed and fabricated on the wafer.

11. Wafer pin test process: Each die is tested for its electrical characteristics with a pin test instrument, and unqualified dies are discarded.

Chip packaging test

Package testing is the packaging and testing of the above-mentioned wafer manufacturing process, in which packaging refers to the process of processing wafers that pass the test to get the chip, and testing is the detection of defective chips, including the wafer test and finished product test before packaging.

Packaging and testing are crucial steps for the finished chip as the last mile before chip production. Packaging can play a role in the protection, support, connection, heat dissipation and reliability of the chip, while testing can ensure the quality of the chip, and even improve the quality of shipments to avoid the flow of defective chips. Specifically, the packaging and testing steps are mainly divided into.

1. Backside thinning: the backside of the wafer is thinned to reach the thickness required for packaging.

2. Wafer cutting: cut the wafer into individual Dice, and then clean the Dice.

3. Light inspection: check if there is scrap.

4. Chip bonding: chip bonding, silver paste curing (to prevent oxidation), lead soldering.

5. Injection moulding: prevent external shock, encapsulate the product with EMC (plastic sealing material) during heating and hardening.

6. Laser typing: engrave the product's production date, batch, etc.

7. High-temperature curing: Protect the internal structure of IC and eliminate internal stress.

8. De-spill material: trim the edges.

9. Plating: Improve conductivity and enhance solderability.

10. Slicing and forming to check the scrap.

11. Chip testing: divided into general testing and special testing. General testing is to test the electrical characteristics of the chip, according to its electrical characteristics are divided into different levels. The special test is a targeted special test to see if it can meet customers' special needs.

12. Test qualified products labelled with specifications, models and factory dates and packaged to leave the factory.


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